A BUILT-IN TEST CIRCUIT FOR DETECTING OPEN INTERCONNECTS IN 3D ICS

Nur Hadi, Widianto Widianto, Hiroyuki Yotsuyanagi, Masaki Hashizume

Abstract


A built-in test circuit is proposed to detect an open interconnect between dies in a 3D IC. A test method is based on large supply current will flow to the IC when a test signal is provided to the test circuit. The test signal consists of an AC voltage signal with a DC offset voltage. Feasibility of the test circuit is examined using a Spice simulation. The simulation results show that the open interconnect can be detected and located at a test speed 2 MHz.

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References


E. J Marinissen, “Challenges in Testing TSV-Based Stacked ICs: Test Flows, Test Contents, Test Access”, Proc. Of APCCAS, pp. 544-547, 2010.

Widianto, H. Yotsuyanagi, A. Ono, M. Takagi, and M. Hashizume, “A Built-in Test Circuit for Open Defects at Interconnect between Dies in 3D ICs”, IEEE International 3D System Integration Conf. P-2-31,pp. 1-5, 2012.




DOI: https://doi.org/10.22219/sentra.v0i1.2090

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Fakultas Teknik

Universitas Muhammadiyah Malang Kampus III

Jl. Raya Tlogomas 246 Malang, 65144