IDDQ TESTING FOR DETECTING RESISTIVE OPEN DEFECTS IN HCMOS LOGIC ICS

Widianto Widianto, Lailis Syafaah, Nurhadi Nurhadi

Abstract


 Resistive open defects may occur at an input gate in a HCMOS logic IC. The defects may be caused by an opened metal line and may degrade performances of the IC. An IDDQ testing is proposed to detect the defects. The testing is based on measuring a quiescent supply current IDDQ value which flows to the IC. The defective IC is detected by flowing the larger IDDQ value compared to the defect-free IC. Feasibility of the testing is implemented in the IC designed by a SPICE library of NXP semiconductor Co. Ltd and is examined using a SPICE simulation of LTSpiceIV. Simulation results show that the resistive open defects may be detected by the IDDQ testing.

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References


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DOI: https://doi.org/10.22219/sentra.v0i3.1494

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